1. Field of the Invention
The present invention relates to the design of analog to digital converters (ADCs), and more specifically to a method and apparatus for increasing the signal to noise ratio (SNR) performance of successive approximation type analog to digital converters (ADCs) without compromising throughput performance substantially
2. Related Art
Analog to digital converters (ADCs) are used to generate a sequence of digital codes representing the signal level of an analog signal as is well known in the relevant art. ADCs often employ successive approximation principle (SAP) for such a conversion. ADCs implemented using SAP are generally referred to as SAR (successive approximation register) ADCs as a register is used to store the codes used to generate an intermediate analog signal.
In a typical SAP based implementation, each bit of a digital code (with the digital code representing a sample of the analog signal) is determined in a single iteration, starting from the most significant bit. To determine the most significant bit, the most significant bit is set to a specific logical value (e.g., 1) and the following bits to the other logical value (0), and the resulting number is converted to the intermediate analog signal (generally using a digital to analog converter (DAC), contained in the ADC). Assuming the specific logical value equals 1, the value of the most significant bit of the digital code is determined to equal 0 if the sample of the analog signal has less voltage than the intermediate analog signal, or else to 1. The next significant bit may be set to 1 (while setting the most significant bit to the determined value) and the following bits to 0, and the resulting number is used to generate a new intermediate analog signal.
The new intermediate analog signal is compared with the sample of the analog signal to determine the corresponding (next significant) bit of the digital code. The approach is continued until all the bits of the digital code are determined. Other digital codes representing an analog signal may be generated at a desired sampling interval.
One parameter of general interest in relation to ADCs is signal-to-noise-ratio (SNR). A high SNR generally implies that the generated digital codes are less susceptible to noise, and a low SNR implies that the digital codes would vary with the noise. Accordingly, a high SNR is generally desirable in several environments.
One source of such noise is the noise components introduced by various components (e.g., transistors) which implement the SAP approach. Such introduced noise is often random in nature, and it is desirable to generate digital codes which are not affected by such noise.
In one prior approach of increasing SNR, multiple temporary codes are generated from a portion of an input analog signal representing the same digital code, and the multiple temporary codes are averaged to generate the digital code. The averaging generally effectively reduces the noise components, as is well known in the relevant arts.
One problem with such an approach is that the throughput of the ADC may be reduced due to the generation of multiple temporary codes. Throughput generally refers to the number of digital codes provided at the output of an ADC. For example, if an ADC converts analog signal at a rate of 1 MSPS (Mega samples per second) and two temporary codes are averaged to generate a single digital code, the throughput of the ADC may be reduced to 500 KSPS (Kilo samples per second).
By using more number of temporary codes to generate each digital code, the SNR of an ADC can be increased further. However, the throughput of the ADC may be reduced by a factor equaling the number of temporary codes used. Such degradation in throughput performance may be undesirable, at least in some environments. What is therefore needed is a method and apparatus to provide high SNR without substantially reducing throughput performance of successive approximation type ADCs.